Arithmetic core Design done,Specification doneWishBone Compliant: NoLicense: GPLDescriptionA 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.)The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells in a 0.35Micron standard CMOS process using the properties of Galois Fields and has been conceived as a 'free' IP.Features- 5 independent channels @ 4Gbps each- Works (simulations) with a standar Aug 8, 2013 VHDL Stable GPL. Arithmetic core n done,FPGA provenWishBone Compliant: NoLicense: GPLDescriptionThis is 8-bit microprocessor with 5 instructions. It is based on 8080 architecture.

This architecture called SAP for Simple-As-Possible computer. It very useful design which introduces most of the basic and fundamental ideas behind computer operation.This design could be used for instruction classes for undergraduate classes or specific VHDL classes. This processor is based on the 8080 architecture, therefore, it could be upgraded step by step to integrate further facilities. It is very exciting challenge for the students to do so. Apr 11, 2012 VHDL Stable GPL. Arithmetic core done,FPGA proven,Specification doneWishBone Compliant: NoLicense: LGPLDescriptionThis is crypto core with AMBA support APB based on datasheet fomAES_SPECIf you liked our work is want to help contribute to the future progress of others who have seen help us by donating.GITHUB: git clone is a group of people working with integrated circuits in Latin America that have done some work with integrated circuits or participated in training in the part of the digital flow. We hope that our IPs are also vital in any way the proposal for those who want to use i Mar 9, 2015 Verilog Stable LGPL.

Arithmetic core n doneWishBone Compliant: NoLicense: LGPLDescriptionA fast (single-cycle) base-2 antilog function.Need an electronic design solution? Visitrun quite as fast as my Log code: 166MHz, vs. 250MHz for the log. Registering the input would bring that up. Takes about the same resources as the log.To do a single-cycle square-root, first take the log.

Then, divide that result by 2 (shift), and take the antilog. Tada.If you use this, please write and tell me about it! Jan 28, 2011 Verilog Stable LGPL. Arithmetic core mpliant: NoLicense:DescriptionThese cores provide a simple means of converting between binary and BCD in hardware. Written in Verilog, with parameters for the input and output widths, these simple cores illustrate the use of functions in Verilog for performing operations that are not easy to do any other way in a fully parameterized (scalable) block of logic.There are two conversions: binary_to_bcd and bcd_to_binary.

These operate serially, requiring one clock per binary bit used in the conversion.The method used for the conversion from base 2 to base 10 is what I call a 'binary coded decim Dec 23, 2009 Unknow Stable Unknown. Arithmetic core e,FPGA proven,Specification doneWishBone Compliant: NoLicense: BSDIntroductionA cellular automata (CA) is a discrete model that consists of a grid (1D, 2D, 3D ) with objects called cells. Each cell can be in one of a given set of states (on and off, different colours etc).

Download the free trial version below to get started. Double-click the downloaded file to install the software. Warning: Invalid argument supplied for foreach() in /srv/users/serverpilot/apps/jujaitaly/public/index.php on line 447.

Each cell has a set of cells in close proximity (neighbours). Given the current internal state of a cell, the states of the neighbour cells and a given set of update rules the next state of a cell can be determined.The ca_prng IP-core implements a 1D binary cellular automata with wrap around at the edges (i.e. The d Dec 20, 2009 Verilog Stable BSD. Arithmetic core ant: NoLicense:DescriptionCores are generated fromConfluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C.

Seewww.confluent.orgfor more info.Cordics (COordinate Rotation DIgital Computers) perform arbitrary phase rotations of complex vectors and are often used to calculate trigonometric functions and vector magnitudes.FeaturesEach file is stand-alone and represents a specific configuration.The 4 parameters are:- Rotation or Vector Mode- Vector Precision- Angle Precision- Number of Cordic StagesAll designs Dec 20, 2009 Unknow Stable Unknown. Arithmetic core: NoLicense:DescriptionCores are generated fromConfluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C.

SeeConfluentfor more info.The Fast Fourier Transform converts time or spacial information into the frequency domain and is one of the most popular DSP algorithms.FeaturesThe FFT architecture is pipelined on a rank basis; each rank hasits own butterfly and ranks are isolated from each other usingmemory interleavers. This FFT can perform calculations oncontinuous streaming data (one data set right after a May 18, 2012 Unknow Stable Unknown.

Download T-link Console Software on this page. Arithmetic core pecification doneWishBone Compliant: NoLicense: LGPLDefinitionA Complex arithmetic library for arithmetic operations is needed in many signal processing applications. This project will present a complex operations library for SystemC based designs. Some of the operations like multiplication, division and square root are based on Cordic algorithms in order to reduce the resources needed for implementation. Eventhough the library is based on the complex library of the Agility Compiler Software but nearly all of the operations were modified and improved. The operations included within this projec Dec 20, 2009 SystemC Alpha LGPL.

Arithmetic core atus:PlanningAdditional info:WishBone Compliant: NoLicense: LGPLDescriptionGaussian Pseudo-random Number Generator is a fix-point entity implemented with VHDL, used for generating complex Gaussian pseudo-random numbers. The generator can be further divided into two stages. The first stage is a uniform pseudo-random number generator called Mersenne Twister, and the second is a conversion stage. Mersenne Twister provides uniform pseudo-random number sequence with an astronomical period of 2^19937-1 up to 32-bit accuracy, using only 624 words working area [1]. A conversion model was built upon Me Dec 21, 2011 VHDL Planning LGPL.

Arithmetic core GA provenWishBone Compliant: NoLicense: GPLDescriptionThe CORDIC algorithm is an iterative algorithm to evaluate many mathematical functions, such as trigonometrically functions, hyperbolic functions and planar rotations.Core DescriptionAs the name suggests the CORDIC algorithm was developed for rotating coordinates, a piece of hardware for doing real-time navigational computations in the 1950's. The CORDIC uses a sequence like successive approximation to reach its results. The nice part is it does this by adding/subtracting and shifting only.Suppose we want to rotate a point(X,Y) by an an Jan 8, 2013 VHDL Stable GPL.

Arithmetic core pliant: NoLicense: LGPLDescriptionThis core is a low latency divider that works by caching reciprocal values, then using a multiply to perform the divide rather than the usual divide operation. On first encountering a divide operation the reciprocal of the divisor is calculated, this takes the same amount of time as a normal divide. The next time the same divide is encountered the pre-calculated reciprocal is used. Reciprocals are stored in a small cache similar to a processor data cache.a/b is the same as a * 1/bIn many cases the divisor 'b' remains the same within a loop. 1/b can be calculat Feb 12, 2013 Verilog Alpha LGPL. Arithmetic core icense:DescriptionRecent advances in communications and networking technologies have made it possible that many applications use digital videos such as teleconferencing and multimedia communications.

These applications require a very large bit-rate if being handled without compression. Most video compression standards such as HDTV, H.261, JPEG and MPEG use Discrete Cosine Transform (DCT) as a standard transform-coding scheme.Discrete Cosine Transform is decomposing the signal into weighted sums of cosine harmonics; unlike DCT, Discrete Fourier Transform decomposes the signal into weighted sums Jul 26, 2013 Unknow Beta Unknown. Arithmetic core proven,Specification doneWishBone Compliant: NoLicense:DescriptionNEW: 12 bit input MDCT version created by Emrah Yuce has been added to project downloads.Parallel synthesizable implementation of 2D DCT in VHDL. Currently works on 8 bit input data using 12 bit DCT coefficients (12-bit DCT output).

Multiplier-less design, parallel distributed arithmetic with butterfly computation used instead. Implementation done as row-column decomposition, two 1D DCT units and transpose matrix between them (double buffered as ping-pong buffer for performance). Latency (time between first 8 bit input data is Mar 7, 2009 VHDL Stable Unknown. Arithmetic core oneWishBone Compliant: NoLicense:Features- The unit is designed to be synchronous to one global clock. All registers are updated on the rising edge of the clock.- All registers can be reset with one global reset.- The multiply operation is broken up to take advantage of the 25 x 18 multiply blocks in the Virtex5 DSP48E slices. The 25 x 18 multiply twos complement block will perform a 24 x 17 unsigned multiply, so it takes 9 DSP48E slices to perform the 53 x 53 bit multiply required to multiply two double-precision floating point numbers.- fpu_double.v is the top-level module.

The input sign Dec 20, 2009 Verilog Alpha Unknown. Arithmetic core nfo:WishBone Compliant: NoLicense: LGPLDescriptionIntroduction:From my thesis: Low-Density Parity Check (LDPC) coding is a form of error coding introduced by Gallager that can achieve performance close to the Shannon limit, exceeding the performance of Turbo codes. The coding scheme was introduced in the early 1960€™s, but has gained favor recently due to excellent performance and lack of patent rights. Several recent standards include optional or mandatory LDPC coding methods; among these is the second generation Digital Video Broadcasting standard for satellite applications (DVB Dec 3, 2010 Verilog Planning LGPL. Arithmetic core WishBone Compliant: NoLicense: GPLComments# ECPU 0.1.alpha# ==============## Background# ========# Resurrected university project originally written in VHDL.# Converted to Verilog by hand and fixed bugs.## Modifications made in verilog post-conversion:# - New barrel shifter# - Reviewed opcode list# - Enhanced testbench to allow for random stimulus (verilog only tb)# - Tested using Icarus## Currently checking for synthesis:# - Passes synthesis checks using 'veriwell. +synopsys'## Features# ========# * 15 working opcodes/functions:# cADD_AB# cINC_A# cINC_B# cSUB_AB# cCMP_ Dec 20, 2009 Verilog Beta GPL. Arithmetic core GA proven,Specification doneWishBone Compliant: NoLicense: LGPLDescriptionThe Elliptic Curve Group core is for computing the addition of two elements in the elliptic curve group, and the addition of $c$ identical elements in the elliptic curve group.The elliptic curve is super-singular $E:y^2=x^3-x+1$ in affine coordinates defined over a Galois field $GF(3^m)$, $m=97$, whose irreducible polynomial is $x^97+x^12+2$.The elliptic curve group is the set of solutions $(x,y)$ over $GF(3^m)$ to the equation of $E$, together with an additional point at infinity, denoted $O$.

An element in the elliptic Apr 18, 2012 Verilog Stable LGPL. Arithmetic core rovenWishBone Compliant: NoLicense: GPLDescriptionQuadratic_func is a fully pipelined quadratic polynomial that computes the relation y = ax^2 + bx + c. On each rising-edge of the clock (when en is high), the coefficients and input x term are sampled at the function inputs. The result has a latency of 3 clock cycles. All inputs to the function are 8-bit signed fractions, with the generic parameter 'fw' specifying the number of fraction bits. The output result is a 24-bit signed fraction.

If integer arithmetic is preferred, then the parameter fw should be set to 0. For larger bit-widths, t Jul 26, 2011 VHDL Stable GPL.

Arithmetic core PGA provenWishBone Compliant: NoLicense:DescriptionThis Floating Point units were developed as part of the HAVOC project. The Design schematics and related files can be browsed at the FPU repository, or downloaded as a separate file from the FP units home page.The FP Adder is a single-precision, IEEE-754 compilant, signed adder/substractor. It includes both single-cycle and 6-stage pipelined designs. The design is fully synthesizable and has been tested in a Xilinx Virtex-II XC2V3000 FPGA, occupying 385 CLBs and with a theoretical maximum operating frecuency of 6MHz for the single-cycle desig Feb 23, 2012 VHDL Stable Unknown. Arithmetic core ne Compliant: NoLicense: LGPLDescriptionThis implementation project proposes a practical implementation of a Median Filter architecture focused in low-cost FPGA devices.

The architecture is based on the research presented in the following paper:but we do not have time to develop a proper architecture document. However the paper presents a brief and at the same time complete description for this implementation design. Mar 21, 2014 Verilog Stable LGPL. Arithmetic core hBone Compliant: NoLicense:DescriptionThis is a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic operations on floating point numbers.

The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in hardware and software.Features- FPU supports the following arithmetic operations:-Add-Subtract-Multiply-Divide-Square Root- For each operation the following rounding modes are supported:-Round to nearest even-Round to zero-Round up-Round down- Pipelined to achieve high operating frequenc Sep 9, 2014 VHDL Stable Unknown. Arithmetic core WishBone Compliant: NoLicense:DescriptionIEEE-754 compliant double-precision floating point unit.

4 operations (addition, subtraction, multiplication, division) are supported, as are the 4 rounding modes (nearest, 0, +inf, -inf). This unit also supports denormalized numbers, which is rare because most floating point units treat denormalized numbers as zero. The unit can run at clock frequencies up to 185 MHz for a Virtex5 target device.Features- The unit is designed to be synchronous to one global clock.

All registers are updated on the rising edge of the clock.- All registers can be reset wi Oct 11, 2014 VHDL Alpha Unknown. Arithmetic core Compliant: NoLicense: LGPLDescriptionFT816 floating point accelerator consists of two ninety-six bit floating point accumulators between which floating point or fixed point operations occur. Basic operations include ADD, SUB, MUL, DIV, FIX2FLT, FLT2FIX, SWAP, NEG and ABS. The floating point accumulators operate as a memory mapped device placed by default between $FEA200 and $FEA2FF. The floating point accelerator communicates through a byte wide data port and twenty-four bit address port. It was intended for use primarily with smaller byte oriented cpu€™s like the 65xx, 68xx series Dec 9, 2014 Verilog Alpha LGPL.

Arithmetic core GA proven,Specification doneWishBone Compliant: NoLicense: LGPLDescriptionThe Gaussian Noise Generator core generates white Gaussian noise of standard normal distribution, which can be used to measure BER to extremely low BER levels (~10-15). The core uses a 64-bit combined Tausworthe generator and an approximation of the inverse normal cumulative distribution function, which obtains a PDF that is Gaussian to up to 9.1ƒ.The core was designed using synthesizable Verilog code and can be delivered as a soft-IP targeted for any FPGA device and ASIC technology. C/MATLAB models and correspondin Feb 1, 2015 Verilog Stable LGPL. Arithmetic core,FPGA provenWishBone Compliant: NoLicense: LGPLDescriptionThis project implements the Galois Linear-feedback Shift Register (LFSR) in VHDL, and can be used for applications such as PRBS generation & synchronisation, CRC computations, scrambling & descrambling, cryptography, etc. This design is very generic / parameterisable, in the sense that it is intelligent enough to be able to 'create' (or generate) the LFSR structure based on user input (a VHDL generic). In thelfsrentity (galois-lfsr.vhdl), there is a generic namedtaps, which allows you to input a vector of tap locations for the L Mar 4, 2014 VHDL Beta LGPL.

Arithmetic core t: NoLicense:DescriptionThis is a collection of synthesizeable hardware dividers. Different types of dividers are available.

All dividers are fully pipelined and provide a 2N by N division every clock cycle. All designs are fully parameteriseable and synthesizeable.The dividers take two inputs Z(2N-bit divident) and D(N-bit divisor), and return Q(N-bit quotient), S(N-bit remainder), div0(division by zero), and ovf(overflow).A sample implementation of a 32/16 bit divider with a remainder output runs at about 82MHz in a Spartan2e100 -6 device and occupies 1132 LUTs (about 47%) and 1736 registers Sep 28, 2011 Unknow Stable Unknown. Arithmetic core Compliant: NoLicense: LGPLReferences1.Yamamoto H., Mori S. Performance of a binary quantized all digital phase-locked loop with a new class of sequential filter//IEEE Trans. 35-45.2.Cessna J.R., Levy D.M. Phase noise and transient times for a binary quantized digital phase-locked loop in which Gaussian noise//IEEE Trans.

94-104.3.Yukawa J., Mori S. A binary quantized digital phase-locked loop//IECE.

Feb 18, 2013 Verilog Stable LGPL. Arithmetic core iant: NoLicense:DescriptionHierarchical Carry Save Algorithm (HCSA) is a modification of well known adder algorithm. Comes as VHDL IP core, shows good timing and small area requirements.The Generic HCSA ALU VHDL IP Core presents an example of HCSA methodology.HCSA adder and ALU with HCSA implemented as VHDL soft IP cores. Algorithm implemetation bases on recursion method.Basic Idea: Every Bit of the Result is calculated twice simultaneously: 1. As if there IS NO carry from LSB ( less significant bit )S(i) = A(i) + B(i) + 0;2. As if these IS a carry from LSBS(i) = A(i) + B(i) Dec 20, 2009 Unknow Stable Unknown.

Arithmetic core mpliant: NoLicense: BSDDescriptionThis project implements a sorter able to sort a continuous stream of data, consisting of records labeled with 'sort keys'.Sorter sorts one record every two clock cycles.Sorter is based on the heap sort algorithm. Efficient implementation is assured thanks to the use of internal dual portRAM in FPGA.The required size of heap is equal to the expected maximum distance between unsorted records in the data stream.Detailed descriptionThe sorter implemented in this project is designed for sorting of stream of constant length records.The main supposed application area Oct 15, 2012 VHDL Beta BSD. Arithmetic core mpliant: NoLicense:DescriptionBefore You readThis is a brief overview of the article about the series of multiplication algorithms. For comparison and estimation of proposed algorithms please refer to the full article.OverviewOperation of multiplication is very important in microelectronics. Each modern microprocessor has this operation within its instruction set, and advanced microprocessors have special multiplication units, that perform multiplication during 1 synchronization period(cycle). Especially valuable multiplication is in DSP processors, where it is practically main operation.

P Dec 20, 2009 Unknow Stable Unknown. Arithmetic core e Compliant: NoLicense: OthersDescriptionHuffman code is used in the most streaming applications.

I have written a Huffman decoder for jpeg pictures. For audio or other data streams the code have to adapt.The state machine is controlled by the jpeg baseline markers.Jpeg header is parsing for quantization and Huffman tables. It is re-programmable in each picture header. The implementation of dynamic Huffman table is very practical. If no information in the header is found the tables from the last picture are used again.In the stream the stuffing bits are removed and recognized the codeword a Nov 14, 2011 VHDL Alpha Others. Arithmetic core neWishBone Compliant: NoLicense: LGPLDescriptionA fast (single-cycle) base-2 log function, based on the description atan electronic design solution? Visituploaded version is in Verilog, with pipelining to maximize the clock frequency.

An example implementation: It takes less than 2% of the smallest CycloneIII, and runs at 250MHz on the IOs. Probably even higher if internal-only. It even fits in a mid-sized CPLD!Second version strips outs the pipelining registers. Simpler if you don't need the throughput.

This one clocks Jan 28, 2011 Verilog Stable LGPL. Arithmetic core:Design done,FPGA provenWishBone Compliant: YesLicense: GPLDescriptionThis IP core allows lossless data compression based on the Lempel-Ziv-Ross-Williams-1 algorithm. Its focus is on high throughput (of uncompressed data) at the expense of an somewhat lower compression ratio. One byte of uncompressed data can be processed at every second clockcycle. A software decoder (decompressor) written in java is included.The core is fully pipelined to allow high clock speeds. 66MHz can easily be achieved on a Spartan6FPGA. This results in a maximum compression throughput of almost 32MBytes/sec.It uses a Dec 19, 2013 VHDL Stable GPL.

Arithmetic core ompliant: NoLicense: LGPLDescriptionThe MESI InterSection Controller (ISC) is a coherence system controller. It supports theMESI coherence protocolfor a cache data consistency. It synchronizes the memory requests of the system masters. It enables to keep the consistency of the data in the memory and in the local caches.This project provides the following elements:A synthesizable controller core with a complete environment of verification, synthesis, and documentation.Instructions for integrating MESI_ISC to a system.A definition and requirements of the system masters.For a detailed descripti Mar 17, 2013 Verilog Alpha LGPL. Arithmetic core Design done,FPGA provenWishBone Compliant: NoLicense: LGPLDescription// number sorting device, sequential, 2*N clocks for N// linear buffer implementation// sequential, stable, can be partly readed, decreasing order// reset is not implemented// see sort_stack_algorithm.png to catch the idea// number sorting, tree-like implementation, sequential,// energy efficient (theoreticaly)// see sort_tree_algorithm.png to catch the ideaArticle(Russian):May 10, 2014 Verilog Beta LGPL.

Arithmetic core pliant: NoLicense:DescriptionBefore You readThis is a brief overview of the article about the series of multiplication algorithms. For comparison and estimation of proposed algorithms please refer to the full article.OverviewOperation of multiplication is very important in microelectronics.

Each modern microprocessor has this operation within its instruction set, and advanced microprocessors have special multiplication units, that perform multiplication during 1 synchronization period(cycle). Especially valuable multiplication is in DSP processors, where it is practically main operation. Pe Jul 17, 2003 Unknow Stable Unknown. Arithmetic core NoLicense:DescriptionThis is synthesizeable radix 4 complex fft processor. Input data width and points are configurable. Output data width = Input data width + 2. Some necessary limited and shift have been done at every butterfly.A sample implementation of a 1024 point 12 bit FFT runs at about 97MHz in a Spartan2e100 -6 device and occupies 1,271 LUTs (about 52%) and 1,144 registers (about 47%) of the device.Features- Data width configurable- Point configurable- Input data during data output- Simulation result has compare with Matlab resultStatus- Design is available in VHDL from OpenCores CVS Sep 30, 2010 Unknow Stable Unknown.

Arithmetic core liant: NoLicense: LGPLDescriptionRay Tracing: A rendering technique that challenges anyone who is interested in Computer Science, Computer Graphics and Digital Systems in General.The Main Goal of this project is to create an engine to Render 3D models. This engine is made over HW/SW. What Im planning to do is to make a RTL generic enough to plug it along with a processor, by means of a bus or any connector the developer wishes.So the RTL's published on this page will describe the HW part of the engine. I don't know, YET, if I'm allowed to upload SW source code. If I am, for sure I will, but Jul 25, 2011 VHDL Mature LGPL.

Arithmetic core ification doneWishBone Compliant: NoLicense: BSDDescriptionSine and cosine table that can be synthesized. Pure VHDL, no other tools orsilicon vendor macros. Pipeline delay can be selected from combinatorialto 10 stages at compile time via a generic.Phase input and sin/cos output widths are automatically determined by theconnected bus. 16 bit phase/18 bit amplitude runs at 230 MHz in Spartan6-3without any optimization efforts. (Just setting 250 MHz as the goal)Also features a programmable pipeline register entity for most basic VHDL types.Pipeline delay can be set from 0 to MAXINT clocksAlso a Feb 26, 2011 VHDL Beta BSD. Arithmetic core Design done,Specification doneWishBone Compliant: NoLicense:Before You ReadThis is a brief overview of the article aboutsingle-clockunsigned integer division algorithm. For comparison and estimation of proposed algorithms please refer to the full article.OverviewNow two division algorithms are wide spread in computing: restoring and non-restoring algorithms.

They consider that both algorithms may be used in sequential calculation scheme, when one digit of the result is achieved during one clock. However there are no principle objections against getting all digits of the quotient and the rema Sep 28, 2011 VHDL Stable Unknown. Arithmetic core hBone Compliant: NoLicense: LGPLDescriptionThe DLX processor is an academic processor described in in John L.

Hennessy and David A. Patterson's Computer Architecture: A Quantitative Approach. Our project aims to offer a decent structural VHDL description of the processor. Moreover, advanced computer architecture features, power management, debug unit, memory management unit and OCP will be added to the project. The final goal of the project is to provide a multi-processor system-on-chip which can support VLSI research or simple embedded application. Oct 31, 2012 VHDL Planning LGPL. Arithmetic core ovenWishBone Compliant: NoLicense: OthersDescriptionThis IP core provides resource efficient ternary adders, i.e., adders with three inputs performing s = x + y + z, for the Altera and Xilinx platforms.Resource efficient means that they need exactly the same resources on modern FPGAs as two-input adders, but are slightly slower.A complete description can be found in the ternary adder documentation:that the used method for the Xilinx ternary is patented (US patent no 7,274,211).

Hence, only private, research or non-commercial use is allowed wi Jan 14, 2015 VHDL Stable Others. Arithmetic core iant: NoLicense: OthersDescriptionkvcordic is a collection of files comprising an implementation of a universal CORDIC algorithm (rotation/vectoring direction, circular/linear/hyperbolic mode) high-level synthesis benchmark by Nikolaos Kavvadias.The design is a universal CORDIC IP core supporting all directions (ROTATION, VECTORING) and modes (CIRCULAR, LINEAR, HYPERBOLIC). The I/O interface is similar to e.g. The CORDIC IP generated by Xilinx Core Generator). It provides three data inputs (xin,yin, zin) and three data outputs (xout,yout, zout) as well as the direction and mode control inputs. Mar 8, 2014 VHDL Beta Others. Arithmetic core mpliant: NoLicense:DescriptionThe serial_divide_uu is a Verilog coded module that performs binary division.

It is fully parameterized, and works in a serial fashion. The number of clock cycles required to complete a divide operation is equal to the number of bits in the quotient plus one.This module has been tested and debugged in actual hardware on a Xilinx XC2S200E FPGA. It was used to divide pulse width by period in a pulse-width-modulation measurement application (ADXL202E 2-axis MEMS accelerometers.)The widths of the signals are configurable by parameters, as follows:M_PP = Bit width o Mar 10, 2013 Unknow Stable Unknown. Arithmetic core Design done,FPGA proven,Specification doneWishBone Compliant: NoLicense: LGPLDescriptionA versatile counter that can be defined as a binary, gray or LFSR counter. Usage include baudrate generator, address generator for FIFO and much more.As a user you edit a define file to make the counter fit your project demands. You the generate a tailored counter. The performance and area can hereby be optimezed for the given applicationPros and cons with different types of counterLFSRextremely low area usagehigh performanceone cycle shorter count cycle compared to binary versionstypically used for interva Jul 14, 2010 Verilog Mature LGPL.

Arithmetic core ication doneWishBone Compliant: NoLicense: LGPLDescriptionCORDIC is the acronym for COordinate Rotation DIgital Computer and allows a hardware efficient calculation of various functions like - atan, sin, cos - atanh, sinh, cosh, - division, multiplication.Hardware efficient means, that only shifting, additions and substractions in combination with table-lookup is required. This makes it suitable for a realization in digital hardware. Good introductions can be found in [1][2][3][4].The following six CORDIC modes are supported:- trigonometric rotation- trigonometric vectoring- linear rotat Mar 30, 2014 VHDL Alpha LGPL PROTOTYPE BOARD. Prototype board e Compliant: NoLicense: GPLDescriptionThis is a small board with the low-cost ACEX FPGA with some SRAM and Flash. It is designed as a module for soft-core CPU development. I've used this board as basis for JOP - the Java processor. JOP still fits into the ACEX 1K50.See some pictures of the board at:schematic and the PCB layout is provided under GPL.Features- Altera ACEX 1K50TC144-3 FPGA- Voltage regulators (3V3, 2V5)- Crystal clock (20 MHz)- 512KB Flash (for FPGA configuration and program)- 128KB Ram- Byteblaster port- Watchdog with LED- EPM7032 PLD to loa Dec 20, 2009 Unknow Stable GPL.

Prototype board iant: NoLicense: LGPLDescriptionTarget of this project is development FPGA and/or FPGA powered real time audio DSP applications. This is Free (like freedom) Hardware project, a PCI card with stand-alone possibility, with high-end digital and analog audio interfaces and MIDI.Possible target development areas will be:- Audio effects and delays- Equalizers (or digital audio filters of any type)- Acoustics correction- Digital crossovers (for loudspeaker systems)- Voice recognition- Synthesizers/samplers- Sample rate converters- Jitter attenuation- Mixing- Studio mastering May 8, 2006 Unknow Planning LGPL. Prototype board one Compliant: NoLicense: OthersDescriptionTheButterfly Lightis an open source, modular FPGA development board. It is comprised of theUSB Cocoonand theSpartan 3E Cocoonwhich paired together create the Butterfly Light FPGA development board. The Butterfly Light is best suited for developers who prefer to create their own daughterboards instead of utilizing the 'Wing' peripheral system. The Butterfly Light exposes the maximum amount of I/O of all available Butterflies. It is also well suited for use with theLogic Analyzersoftware which implements a 100Mhz, 32 channelLogic Analyzer.EAGLE design f Dec 20, 2009 Other Stable Others.

Prototype board o:WishBone Compliant: YesLicense: LGPLDescriptionThis project uses two off the shelf boards and interfaces them. The processor board used is a Olimex LPC-L2294 and the FPGA board is a Terasic DE1. A Olimex ARM-USB-OCD was used to load and debug the code. The boards were cabled together with floppy and hard drive cables. The entire setup cost less than $350. How To Install Reunion Patch Ff7 Walkthrough. The bridge from the wb_async_mem_bridge project is used to interface the External Memory Controller to the Wishbone bus on the FPGA. Currently the SRAM, GPIOs & HEX LED display is connected and there are plans to add the other interfaces Apr 6, 2010 Verilog Alpha LGPL.

Prototype board Compliant: NoLicense:DescriptionEUS FS is an 'open' system board designed for industrial control and data acquisition applications. It is equipped with a 32-bit CPU working @ 200MHz (Etrax FS), Xilinx's gate array (Spartan 3E) and support electronics. A BSP package contains Linux operating system version 2.6, driver for communication with FPGA and peripheral devices. Example FPGA cores are available in source form, along with full board documentation and schematics.Features List- Board dimensions 85 x 55 mm (3.35 x 2.175' )- 200MHz, 32bit Etrax FS processor- Up to 256MB SDRAM- 8 - 64 MB Flash Dec 20, 2009 Unknow Stable Unknown. Prototype board doneWishBone Compliant: NoLicense: GPLShort DescriptionMinMax game tree search with alpha-beta pruning implemented in FPGA.Rules and heuristics implemented for Reversi/Othello game. The system is capable of analyzing ~5M game states/second @50MHz.

(no selective search).RTL design Verilog 2001 compliant.VGA output, pushbuttons input (for playing), using Spartan3E Starter Kit board.General FeaturesTransition from a current game state to another is done in 1cc.Determining all possible transitions from a game state to another is also done in 1cc.Evaluation of one game state is done in 1cc.The heur Dec 6, 2011 Verilog Alpha GPL. Prototype board: NoLicense: BSDNorwegian University of Science and TechnologyThis project came to be because of the course 'TDT4295 - Computer Design, Project', due to theInstitute of Computer and Information ScienceatThe Norwegian University of Science and Technology. The project was supervised by Assoc. Prof.Morten HartmannWhat is this?IGOR is in a complete system including:* A PCB with all the components of the system: FPGA, AVR microcontroller, IO-units, Memory. The works.* An implemented processor running on the FPGA.* Several IO units, connected to the main processor through an AVR mircrocontroller t Jan 6, 2010 VHDL Beta BSD. Prototype board liant: NoLicense: GPLDescriptionThe IIE-PCI Development Platform board is a low cost PCI device card with a programmable logic chip (Altera ACEX), dynamic ram, and expansion capabilities.The main purpose of the IIE-PCI board is to test PCI designs in a educational environment.

Cost was a primary concern. The fabrication cost for the prototype board was U$S 330, if 10 boards are made, the cost will drop to U$S 230 per unit.More information is available at the project website:-(original site in spanish)-Dec 20, 2009 Other Stable GPL. Prototype board: YesLicense:DescriptionThe internal Logic state Analyser (LA) is a simplified version of a standard logic state analyzer, however it is build-in the prototyped circuit and therefore allows for probing internal signals. The LA at first writes probed signals into its internal memory, and then allows for off-line transfer through WISHBONE bus to a PC where the probed data can be watched. As during design prototyping watched signals are very often changed, the LA is mainly intended for FPGAs and works similarly to Xilinx ChipScope.FeaturesInternal memory for on-line data probing and off-line prob Dec 11, 2002 Unknow Beta Unknown. Prototype board done,FPGA proven,Specification doneWishBone Compliant: YesLicense:Description[Keep It Simple,Stupid] Board.The board was evaluated like [or1k/orp project].BOARD consists of two pieces.

One is FPGA board. Another is MOTHER board.The device on the FPGA board is ANY(xilinx or altera.).Only connected specification of the board is important.Board snapshotsMOTHER boardFPGA boardStatusAssemblyIt's planning(more cheap!)EvaluationIt's finished(commit code,RTL8019AS Evaluation is done)SimulationIt's finished(commit code,checkout-test is done)DesignIt's finished(commit code,checkout-test is Dec 20, 2009 Verilog Stable Unknown. Prototype board nt: NoLicense:DescriptionEUS 100LX is an 'open' system board conforming to the PC104 format (90,2mm x 95,9mm) designed for industrial control and data acquisition applications. It is equipped with CPU, gate array and support electronics and comes with Linux operating system version 2.4 or 2.6, driver for communication with FPGA and peripheral devices, Allegro graphics library. Example FPGA cores are available in source form, as well as full board documentation - schematics, layout (available atETRAX 100LX / MCM4+16 CPU- 32 MB SDRAM, 8 - 64 MB F Dec 20, 2009 Unknow Stable Unknown. Prototype board NoLicense:DescriptionMicro FPGA board is a stand alone, low cost, do-it-yourself board.

All components are possible to get from a local electronics shop (with possible exception of Virtex part). Board includes one Xilinx Virtex XCV100 chip.FPGA is loaded from PC via Xilinx XChecker cable and external power supply must be provided. It is designed for debugging and verification process of small units or cores. See a block diagram for details.Status- board is finished and it is fully functionalShematic sourcesSchematic as Adobe PDF documentSchematic in Protel Binary formatLibrary in Protel Binar Mar 10, 2009 Unknow Stable Unknown. Prototype board: NoLicense:Specifications- small form factor (1dm2)- inexpensive surface mount technology (no Ball Grid Array (BGA) chips)- fast 50k gates or bigger FPGA- basic I/O capabilities like RS232 and IRDA- FLASH memory for FPGA configuration and microprocessor code- fast SDRAM for main memory- direct access to important signals through Logic Analyzer connectorsDescriptionOpenCores Reference Platform 1 (OCRP-1) standalone board was designed as a common prototype platform for testing our IP cores.

It has a central FPGA for evaluating and testing IP cores, I/O capabilities, DRAM and FLASH memory. It al Jan 22, 2004 Unknow Stable Unknown. Prototype board t: NoLicense:DescriptionOpenCores Reference Platform 2 (OCRP-2) is full-size length add-in PCI board. It includes two FPGA chips, video D/A and A/D converters, SDRAM memory, FLASH memory, PLD chip, USB, EIA232 and Ethernet PHY chips.

It is designed for a debugging and verification process for several of our cores. See a block diagram for details.One special function of this board is to provide a method for a remote test of cores.

The board will be used via web based interface. It will be possible to download design to the board and use a JAVA based logic analyzer and signal generator to debug Oct 15, 2001 Unknow Planning Unknown. Prototype board iant: NoLicense: OthersDescriptionOMRP (Openpattern Modular Routing Platform) is the first product-oriented project of the OpenPattern company.

The target is to create a new open hardware FPGA-based network router that can be used for mesh wifi networks, as an alternative of ISPs home-gateway, and as a development platform for future open-hardware SoC projects.Features- Open hardware - schematics and HDL sources will be/are released.- Flexible - implement whatever hardware acceleration or protocol you want in the FPGA.- Modular - many standard extension ports are implemented.- Unbrickable - ev Jul 1, 2010 Other Alpha Others. Prototype board t: NoLicense:IntroductionAll electronics designers, students and researchers are always trying to test their ideas and check its performance before punishing it. Several kinds of test prototype boards are used for this purpose.

Usually these boards are either very expensive and has either more or less features than what the designer need. For this reason the idea of designing a simple and open design board is going to be available for anyone for almost nothing and he/she can customize it for his/her specific needs. The design of this board is intended to be an open design and to use free and o Dec 20, 2009 Unknow Planning Unknown.

Prototype board: NoLicense:IntroductionAs you know, we have lots of free IP cores here, and we€™ll have more coming soon. We have to use these cores otherwise they are invaluable. For this reason the idea of designing serials and open design boards are going to be available for any designers around the world.ObjectiveThis project is intended to:- To design schematic can deal with analog signal and transport through Ethernet.- To implementation CPU core and Ethernet core to one FPGA chip- To program the necessary operation system and application software to achieve the goal.- To build the prototype Oct 15, 2001 Unknow Planning Unknown.

Prototype board Compliant: NoLicense:DescriptionOpensource OpenRisc Development Board. All CADsoft Eagle design files available to recreate the board using EagleLite, a freeware PCB design tool. Uses the largest Cyclone 2 device available in a QFP package, thus allowing larger RTL designs to be ported, and at the same time allowing easier PCB design and board assembly. Board design is double sided, and can be manufactured using low cost batch PCB services. But despite only being double layer, it has an almost continuous bottom side ground plane.A complete system consists of two separate boards;- Main FPG Dec 29, 2008 Unknow Stable Unknown.

To link to this poem, put the URL below into your page: Song of Myself by Walt Whitman Walt Whitman: Song of Myself The DayPoems Poetry Collection, editor Click to submit poems to DayPoems, comment on DayPoems or a poem within, comment on other poetry sites, update links, or simply get in touch.. Poetry Whirl Indexes Poetry Places Nodes powered by Open Directory Project at dmoz.org DayPoems Favorites, a huge collection of books as text, produced as a volunteer enterprise starting in 1990. This is the source of the first poetry placed on DayPoems., exactly what the title says, and well worth reading.: 'If a guy somewhere in Asia makes a blog and no one reads it, does it really exist?' , miniature, minimalist-inspired sculptures created from industrial cereamics, an art project at Lewis and Clark College in Portland, Oregon., More projects from Portland, Furby, Eliza, Mr_Friss and Miss_Friss., a Portland, Oregon, exhibit, Aug.

5, 2004, at Disjecta. D a y P o e m s * D a y P o e m s * D a y P o e m s * D a y P o e m s * D a y P o e m s * D a y P o e m s * D a y P o e m s Won't you help support DayPoems? Song of Myself By 1819-1892 1 I celebrate myself, and sing myself, And what I assume you shall assume, For every atom belonging to me as good belongs to you. I loafe and invite my soul, I lean and loafe at my ease observing a spear of summer grass. My tongue, every atom of my blood, form'd from this soil, this air, Born here of parents born here from parents the same, and their parents the same, I, now thirty-seven years old in perfect health begin, Hoping to cease not till death. Creeds and schools in abeyance, Retiring back a while sufficed at what they are, but never forgotten, I harbor for good or bad, I permit to speak at every hazard, Nature without check with original energy.

2 Houses and rooms are full of perfumes, the shelves are crowded with perfumes, I breathe the fragrance myself and know it and like it, The distillation would intoxicate me also, but I shall not let it. The atmosphere is not a perfume, it has no taste of the distillation, it is odorless, It is for my mouth forever, I am in love with it, I will go to the bank by the wood and become undisguised and naked, I am mad for it to be in contact with me.